Further parse AHCI information.
Send an IDENTIFY command to each drive and set up a hook to handle interrupts.
This commit is contained in:
Drew Galbraith
parent
4e1888bd24
commit
0f0e39d1e9
25 changed files with 721 additions and 90 deletions
157
sys/denali/ahci/ahci.h
Normal file
157
sys/denali/ahci/ahci.h
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@ -0,0 +1,157 @@
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#pragma once
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#include <stdint.h>
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struct PciDeviceHeader {
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uint16_t vendor_id;
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uint16_t device_id;
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uint16_t command_reg;
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uint16_t status_reg;
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uint8_t revision;
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uint8_t prog_interface;
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uint8_t subclass;
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uint8_t class_code;
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uint8_t cache_line_size;
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uint8_t latency_timer;
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uint8_t header_type;
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uint8_t bist;
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uint32_t bars[5];
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uint32_t abar;
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uint32_t reserved0;
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uint32_t subsystem_id;
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uint32_t expansion_rom;
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uint8_t cap_ptr;
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uint8_t reserved1[7];
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uint8_t interrupt_line;
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uint8_t interrupt_pin;
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uint8_t min_grant;
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uint8_t max_latency;
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} __attribute__((packed));
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struct PciMsiCap {
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uint8_t cap_id;
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uint8_t next_offset;
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uint8_t message_control;
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uint8_t reserved;
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uint64_t message_address;
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uint16_t message_data;
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};
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struct AhciHba {
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uint32_t capabilities;
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uint32_t global_host_control;
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uint32_t interrupt_status;
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uint32_t port_implemented;
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uint32_t version;
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uint32_t ccc_ctl; // 0x14, Command completion coalescing control
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uint32_t ccc_pts; // 0x18, Command completion coalescing ports
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uint32_t em_loc; // 0x1C, Enclosure management location
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uint32_t em_ctl; // 0x20, Enclosure management control
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uint32_t capabilities_ext;
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uint32_t bohc; // 0x28, BIOS/OS handoff control and status
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} __attribute__((packed));
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struct AhciPort {
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uint64_t command_list_base;
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uint64_t fis_base;
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uint32_t interrupt_status;
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uint32_t interrupt_enable;
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uint32_t command;
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uint32_t reserved;
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uint32_t task_file_data;
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uint32_t signature;
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uint32_t sata_status;
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uint32_t sata_control;
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uint32_t sata_error;
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uint32_t sata_active;
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uint32_t command_issue;
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uint32_t sata_notification;
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uint32_t fis_based_switching_ctl;
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uint32_t device_sleep;
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} __attribute__((packed));
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struct CommandHeader {
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uint16_t command;
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uint16_t prd_table_length;
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uint32_t prd_byte_count;
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uint64_t command_table_base_addr;
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uint64_t reserved1;
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uint64_t reserved2;
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} __attribute__((packed));
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struct CommandList {
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CommandHeader command_headers[32];
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} __attribute__((packed));
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struct PhysicalRegionDescriptor {
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uint64_t region_address;
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uint32_t reserved;
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// bit 0 must be one.
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// 21:0 is byte count
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// 31 is Interrupt on Completion
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uint32_t byte_count;
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};
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struct CommandTable {
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uint8_t command_fis[64];
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uint8_t atapi_command[16];
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uint8_t reserved[48];
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PhysicalRegionDescriptor prds[65535];
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} __attribute__((packed));
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typedef enum {
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FIS_TYPE_REG_H2D = 0x27, // Register FIS - host to device
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FIS_TYPE_REG_D2H = 0x34, // Register FIS - device to host
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FIS_TYPE_DMA_ACT = 0x39, // DMA activate FIS - device to host
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FIS_TYPE_DMA_SETUP = 0x41, // DMA setup FIS - bidirectional
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FIS_TYPE_DATA = 0x46, // Data FIS - bidirectional
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FIS_TYPE_BIST = 0x58, // BIST activate FIS - bidirectional
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FIS_TYPE_PIO_SETUP = 0x5F, // PIO setup FIS - device to host
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FIS_TYPE_DEV_BITS = 0xA1, // Set device bits FIS - device to host
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} FIS_TYPE;
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struct DmaFis {};
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struct PioSetupFis {};
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struct HostToDeviceRegisterFis {
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uint8_t fis_type; // FIS_TYPE_REG_H2D
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uint8_t pmp_and_c;
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uint8_t command; // Command register
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uint8_t featurel; // Feature register, 7:0
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// DWORD 1
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uint8_t lba0; // LBA low register, 7:0
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uint8_t lba1; // LBA mid register, 15:8
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uint8_t lba2; // LBA high register, 23:16
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uint8_t device; // Device register
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// DWORD 2
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uint8_t lba3; // LBA register, 31:24
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uint8_t lba4; // LBA register, 39:32
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uint8_t lba5; // LBA register, 47:40
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uint8_t featureh; // Feature register, 15:8
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// DWORD 3
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uint16_t count;
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uint8_t icc; // Isochronous command completion
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uint8_t control; // Control register
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// DWORD 4
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uint32_t reserved; // Reserved
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};
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struct DeviceToHostRegisterFis {};
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struct SetDeviceBitsFis {};
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struct ReceivedFis {
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DmaFis dma_fis;
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uint32_t reserved0;
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PioSetupFis pio_set_fis;
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uint32_t reserved1[3];
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DeviceToHostRegisterFis device_to_host_register_fis;
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uint32_t reserved2;
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SetDeviceBitsFis set_device_bits_fis;
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uint8_t unknown_fis[64];
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} __attribute__((packed));
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108
sys/denali/ahci/ahci_device.cpp
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108
sys/denali/ahci/ahci_device.cpp
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@ -0,0 +1,108 @@
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#include "ahci/ahci_device.h"
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#include <mammoth/debug.h>
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#include <string.h>
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#include <zcall.h>
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AhciDevice::AhciDevice(AhciPort* port) : port_struct_(port) {
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if ((port_struct_->sata_status & 0x103) != 0x103) {
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return;
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}
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uint64_t cl_page = port_struct_->command_list_base & (~0xFFF);
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uint64_t fis_page = port_struct_->fis_base & (~0xFFF);
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if (cl_page != fis_page) {
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crash("Non adjacent cl & fis", Z_ERR_UNIMPLEMENTED);
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}
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check(ZMemoryObjectCreatePhysical(cl_page, 0x1000, &vmmo_cap_));
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uint64_t vaddr;
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check(ZAddressSpaceMap(Z_INIT_VMAS_SELF, 0, vmmo_cap_, &vaddr));
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uint64_t cl_off = port_struct_->command_list_base & 0xFFF;
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command_list_ = reinterpret_cast<CommandList*>(vaddr + cl_off);
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uint64_t fis_off = port_struct_->fis_base & 0xFFF;
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received_fis_ = reinterpret_cast<ReceivedFis*>(vaddr + fis_off);
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// FIXME: Hacky
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uint64_t ct_off =
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command_list_->command_headers[0].command_table_base_addr & 0xFFF;
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command_table_ = reinterpret_cast<CommandTable*>(vaddr + ct_off);
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port_struct_->interrupt_enable = 0xFFFFFFFF;
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}
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z_err_t AhciDevice::SendIdentify(uint16_t** result) {
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HostToDeviceRegisterFis fis{
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.fis_type = FIS_TYPE_REG_H2D,
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.pmp_and_c = 0x80,
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.command = 0xEC,
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.featurel = 0,
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.lba0 = 0,
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.lba1 = 0,
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.lba2 = 0,
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.device = 0,
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.lba3 = 0,
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.lba4 = 0,
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.lba5 = 0,
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.featureh = 0,
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.count = 0,
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.icc = 0,
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.control = 0,
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.reserved = 0,
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};
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command_list_->command_headers[0].command = (sizeof(fis) / 2) & 0x1F;
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command_list_->command_headers[0].prd_table_length = 1;
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memcpy(command_table_->command_fis, &fis, sizeof(fis));
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port_struct_->command_issue |= 1;
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uint64_t vmmo_cap, paddr;
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RET_ERR(ZMemoryObjectCreateContiguous(512, &vmmo_cap, &paddr));
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command_table_->prds[0].region_address = paddr;
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command_table_->prds[0].byte_count = 512;
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uint64_t vaddr;
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RET_ERR(ZAddressSpaceMap(Z_INIT_VMAS_SELF, 0, vmmo_cap, &vaddr));
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*result = reinterpret_cast<uint16_t*>(vaddr);
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return Z_OK;
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}
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void AhciDevice::DumpInfo() {
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dbgln("Comlist: %lx", port_struct_->command_list_base);
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dbgln("FIS: %lx", port_struct_->fis_base);
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dbgln("Command: %x", port_struct_->command);
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dbgln("Signature: %x", port_struct_->signature);
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dbgln("SATA status: %x", port_struct_->sata_status);
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dbgln("Int status: %x", port_struct_->interrupt_status);
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dbgln("Int enable: %x", port_struct_->interrupt_enable);
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dbgln("Int enable: %x", port_struct_->interrupt_enable);
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// Just dump one command info for now.
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for (uint64_t i = 0; i < 1; i++) {
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dbgln("Command Header: %u", i);
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dbgln("Command %x", command_list_->command_headers[i].command);
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dbgln("PRD Len: %x", command_list_->command_headers[i].prd_table_length);
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dbgln("Command Table %lx",
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command_list_->command_headers[i].command_table_base_addr);
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}
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}
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void AhciDevice::HandleIrq() {
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uint64_t int_status = port_struct_->interrupt_status;
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// FIXME: Probably only clear the interrupts we know how to handle.
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port_struct_->interrupt_status = int_status;
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dbgln("int receieved: %x", int_status);
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}
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29
sys/denali/ahci/ahci_device.h
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29
sys/denali/ahci/ahci_device.h
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#pragma once
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#include <zerrors.h>
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#include "ahci/ahci.h"
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class AhciDevice {
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public:
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AhciDevice() {}
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// Caller retains ownership of the pointer.
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AhciDevice(AhciPort* port_struct);
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void DumpInfo();
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bool IsInit() { return port_struct_ != nullptr && vmmo_cap_ != 0; }
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// Result will point to a 512 byte (256 word array).
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z_err_t SendIdentify(uint16_t** result);
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void HandleIrq();
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private:
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AhciPort* port_struct_ = nullptr;
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uint64_t vmmo_cap_ = 0;
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CommandList* command_list_ = nullptr;
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ReceivedFis* received_fis_ = nullptr;
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CommandTable* command_table_ = nullptr;
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};
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@ -9,13 +9,30 @@ namespace {
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const uint64_t kSataPciPhys = 0xB00FA000;
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const uint64_t kPciSize = 0x1000;
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const uint64_t kGhc_InteruptEnable = 0x2;
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void interrupt_thread(void* void_driver) {
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AhciDriver* driver = static_cast<AhciDriver*>(void_driver);
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dbgln("this %lx", driver);
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driver->InterruptLoop();
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crash("Driver returned from interrupt loop", Z_ERR_UNIMPLEMENTED);
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}
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} // namespace
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z_err_t AhciDriver::Init() {
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RET_ERR(LoadPciDeviceHeader());
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RET_ERR(LoadCapabilities());
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dbgln("ABAR: %x", pci_device_header_->abar);
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dbgln("Interrupt line: %x", pci_device_header_->interrupt_line);
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dbgln("Interrupt pin: %x", pci_device_header_->interrupt_pin);
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RET_ERR(RegisterIrq());
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RET_ERR(LoadHbaRegisters());
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dbgln("Version: %x", ahci_hba_->version);
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ahci_hba_->global_host_control |= kGhc_InteruptEnable;
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RET_ERR(LoadDevices());
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DumpCapabilities();
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DumpPorts();
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return Z_OK;
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@ -26,7 +43,7 @@ void AhciDriver::DumpCapabilities() {
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uint32_t caps = ahci_hba_->capabilities;
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dbgln("Num Ports: %u", (caps & 0x1F) + 1);
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dbgln("Num Command Slots: %u", (caps & 0x1F00) >> 8);
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dbgln("Num Command Slots: %u", ((caps & 0x1F00) >> 8) + 1);
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if (caps & 0x20) {
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dbgln("External SATA");
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}
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@ -97,33 +114,33 @@ void AhciDriver::DumpCapabilities() {
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if (caps & 0x10) {
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dbgln("Aggressive device sleep management");
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}
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dbgln("Control %x", ahci_hba_->global_host_control);
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}
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void AhciDriver::DumpPorts() {
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dbgln("Ports implemented %x", ahci_hba_->port_implemented);
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uint64_t port_index = 0;
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uint32_t ports_implemented = ahci_hba_->port_implemented;
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while (ports_implemented) {
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if (!(ports_implemented & 0x1)) {
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ports_implemented >>= 1;
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port_index++;
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for (uint64_t i = 0; i < 6; i++) {
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AhciDevice& dev = devices_[i];
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if (!dev.IsInit()) {
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continue;
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}
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uint64_t port_addr =
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reinterpret_cast<uint64_t>(ahci_hba_) + 0x100 + (0x80 * port_index);
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AhciPort* port = reinterpret_cast<AhciPort*>(port_addr);
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dbgln("");
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dbgln("Port %u:", port_index);
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dbgln("Comlist: %lx", port->command_list_base);
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dbgln("FIS: %lx", port->fis_base);
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dbgln("Command: %x", port->command);
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dbgln("Signature: %x", port->signature);
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dbgln("SATA status: %x", port->sata_status);
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dbgln("Port %u:", i);
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dev.DumpInfo();
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}
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}
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ports_implemented >>= 1;
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port_index++;
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void AhciDriver::InterruptLoop() {
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dbgln("this %lx", this);
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while (true) {
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uint64_t type, bytes, caps;
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check(ZPortRecv(irq_port_cap_, 0, 0, 0, 0, &type, &bytes, &caps));
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for (uint64_t i = 0; i < 6; i++) {
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if (devices_[i].IsInit()) {
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devices_[i].HandleIrq();
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}
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}
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}
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}
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@ -137,6 +154,46 @@ z_err_t AhciDriver::LoadPciDeviceHeader() {
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return Z_OK;
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}
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z_err_t AhciDriver::LoadCapabilities() {
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if (!(pci_device_header_->status_reg & 0x10)) {
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dbgln("No caps!");
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return Z_ERR_INVALID;
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}
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uint8_t* base = reinterpret_cast<uint8_t*>(pci_device_header_);
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uint16_t offset = pci_device_header_->cap_ptr;
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do {
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uint16_t* cap = reinterpret_cast<uint16_t*>(base + offset);
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switch (*cap & 0xFF) {
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case 0x01:
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dbgln("Power Management");
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break;
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case 0x05:
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dbgln("MSI");
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break;
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case 0x12:
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dbgln("SATA");
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break;
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default:
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dbgln("Unrecognized cap");
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break;
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}
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offset = (*cap & 0xFF00) >> 8;
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} while (offset);
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return Z_OK;
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}
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z_err_t AhciDriver::RegisterIrq() {
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if (pci_device_header_->interrupt_pin == 0) {
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crash("Can't register IRQ without a pin num", Z_INVALID);
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}
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uint64_t irq_num = Z_IRQ_PCI_BASE + pci_device_header_->interrupt_pin - 1;
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RET_ERR(ZIrqRegister(irq_num, &irq_port_cap_));
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dbgln("this %lx", this);
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irq_thread_ = Thread(interrupt_thread, this);
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return Z_OK;
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}
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z_err_t AhciDriver::LoadHbaRegisters() {
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uint64_t vmmo_cap;
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RET_ERR(
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@ -147,3 +204,22 @@ z_err_t AhciDriver::LoadHbaRegisters() {
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ahci_hba_ = reinterpret_cast<AhciHba*>(vaddr);
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return Z_OK;
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}
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z_err_t AhciDriver::LoadDevices() {
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// FIXME: Don't set this up so we hardcode 6 devices.
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for (uint8_t i = 0; i < 6; i++) {
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if (!(ahci_hba_->port_implemented & (1 << i))) {
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continue;
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}
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uint64_t port_addr =
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reinterpret_cast<uint64_t>(ahci_hba_) + 0x100 + (0x80 * i);
|
||||
devices_[i] = AhciDevice(reinterpret_cast<AhciPort*>(port_addr));
|
||||
if (!devices_[i].IsInit()) {
|
||||
continue;
|
||||
}
|
||||
dbgln("Identify %u", i);
|
||||
uint16_t* identify;
|
||||
devices_[i].SendIdentify(&identify);
|
||||
}
|
||||
return Z_OK;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,69 +1,17 @@
|
|||
#pragma once
|
||||
|
||||
#include <mammoth/thread.h>
|
||||
#include <zerrors.h>
|
||||
|
||||
struct PciDeviceHeader {
|
||||
uint16_t vendor_id;
|
||||
uint16_t device_id;
|
||||
uint16_t command_reg;
|
||||
uint16_t status_reg;
|
||||
uint8_t revision;
|
||||
uint8_t prog_interface;
|
||||
uint8_t subclass;
|
||||
uint8_t class_code;
|
||||
uint8_t cache_line_size;
|
||||
uint8_t latency_timer;
|
||||
uint8_t header_type;
|
||||
uint8_t bist;
|
||||
uint32_t bars[5];
|
||||
uint32_t abar;
|
||||
uint32_t subsystem_id;
|
||||
uint32_t expansion_rom;
|
||||
uint8_t cap_ptr;
|
||||
uint8_t reserved[7];
|
||||
uint8_t interrupt_line;
|
||||
uint8_t interrupt_pin;
|
||||
uint8_t min_grant;
|
||||
uint8_t max_latency;
|
||||
} __attribute__((packed));
|
||||
|
||||
struct AhciHba {
|
||||
uint32_t capabilities;
|
||||
uint32_t global_host_control;
|
||||
uint32_t interrupt_status;
|
||||
uint32_t port_implemented;
|
||||
uint32_t version;
|
||||
uint32_t ccc_ctl; // 0x14, Command completion coalescing control
|
||||
uint32_t ccc_pts; // 0x18, Command completion coalescing ports
|
||||
uint32_t em_loc; // 0x1C, Enclosure management location
|
||||
uint32_t em_ctl; // 0x20, Enclosure management control
|
||||
uint32_t capabilities_ext;
|
||||
uint32_t bohc; // 0x28, BIOS/OS handoff control and status
|
||||
};
|
||||
|
||||
struct AhciPort {
|
||||
uint64_t command_list_base;
|
||||
uint64_t fis_base;
|
||||
uint32_t interrupt_status;
|
||||
uint32_t interrupt_enable;
|
||||
uint32_t command;
|
||||
uint32_t reserved;
|
||||
uint32_t task_file_data;
|
||||
uint32_t signature;
|
||||
uint32_t sata_status;
|
||||
uint32_t sata_control;
|
||||
uint32_t sata_error;
|
||||
uint32_t sata_active;
|
||||
uint32_t command_issue;
|
||||
uint32_t sata_notification;
|
||||
uint32_t fis_based_switching_ctl;
|
||||
uint32_t device_sleep;
|
||||
};
|
||||
#include "ahci/ahci.h"
|
||||
#include "ahci/ahci_device.h"
|
||||
|
||||
class AhciDriver {
|
||||
public:
|
||||
z_err_t Init();
|
||||
|
||||
void InterruptLoop();
|
||||
|
||||
void DumpCapabilities();
|
||||
void DumpPorts();
|
||||
|
||||
|
|
@ -71,6 +19,14 @@ class AhciDriver {
|
|||
PciDeviceHeader* pci_device_header_ = nullptr;
|
||||
AhciHba* ahci_hba_ = nullptr;
|
||||
|
||||
AhciDevice devices_[6];
|
||||
|
||||
Thread irq_thread_;
|
||||
uint64_t irq_port_cap_ = 0;
|
||||
|
||||
z_err_t LoadPciDeviceHeader();
|
||||
z_err_t LoadCapabilities();
|
||||
z_err_t RegisterIrq();
|
||||
z_err_t LoadHbaRegisters();
|
||||
z_err_t LoadDevices();
|
||||
};
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue