Further parse AHCI information.
Send an IDENTIFY command to each drive and set up a hook to handle interrupts.
This commit is contained in:
parent
4e1888bd24
commit
0f0e39d1e9
25 changed files with 721 additions and 90 deletions
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@ -19,6 +19,7 @@ add_executable(zion
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object/address_space.cpp
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object/channel.cpp
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object/memory_object.cpp
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object/port.cpp
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object/process.cpp
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object/thread.cpp
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scheduler/context_switch.s
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@ -42,3 +42,11 @@ RefPtr<Channel> Capability::obj<Channel>() {
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}
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return StaticCastRefPtr<Channel>(obj_);
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}
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template <>
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RefPtr<Port> Capability::obj<Port>() {
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if (type_ != PORT) {
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panic("Accessing %u cap as object.", type_);
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}
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return StaticCastRefPtr<Port>(obj_);
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}
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@ -17,6 +17,7 @@ class Capability : public RefCounted<Capability> {
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ADDRESS_SPACE,
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MEMORY_OBJECT,
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CHANNEL,
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PORT,
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};
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Capability(const RefPtr<KernelObject>& obj, Type type, uint64_t id,
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uint64_t permissions)
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@ -43,6 +43,14 @@
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#define Z_CHANNEL_RECV 0x42
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#define Z_CHANNEL_SENDRECV 0x43
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#define Z_PORT_CREATE 0x50
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#define Z_PORT_SEND 0x51
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#define Z_PORT_RECV 0x52
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#define Z_IRQ_REGISTER 0x58
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#define Z_IRQ_PCI_BASE 0x30
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// Debugging Calls.
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#define Z_DEBUG_PRINT 0x10000000
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@ -70,6 +78,10 @@ void ZThreadExit();
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[[nodiscard]] z_err_t ZMemoryObjectCreate(uint64_t size, uint64_t* vmmo_cap);
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[[nodiscard]] z_err_t ZMemoryObjectCreatePhysical(uint64_t paddr, uint64_t size,
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uint64_t* vmmo_cap);
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[[nodiscard]] z_err_t ZMemoryObjectCreateContiguous(uint64_t size,
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uint64_t* vmmo_cap,
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uint64_t* paddr);
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[[nodiscard]] z_err_t ZTempPcieConfigObjectCreate(uint64_t* vmmo_cap,
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uint64_t* vmmo_size);
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@ -83,4 +95,10 @@ void ZThreadExit();
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uint64_t* actual_bytes,
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uint64_t* actual_caps);
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[[nodiscard]] z_err_t ZPortRecv(uint64_t port_cap, uint64_t num_bytes,
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uint8_t* bytes, uint64_t num_caps,
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uint64_t* caps, uint64_t* type,
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uint64_t* actual_bytes, uint64_t* actual_caps);
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[[nodiscard]] z_err_t ZIrqRegister(uint64_t irq_num, uint64_t* port_cap);
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[[nodiscard]] z_err_t ZDebug(const char* message);
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@ -7,7 +7,7 @@
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#include "common/port.h"
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#include "debug/debug.h"
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#define APIC_DEBUG 0
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#define APIC_DEBUG 1
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namespace {
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@ -17,6 +17,7 @@ namespace {
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const uint64_t kEoiOffset = 0xB0;
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// FIXME: parse these from madt.
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constexpr uint64_t kLApicBase = 0xFEE0'0000;
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constexpr uint64_t kIoApicAddr = 0xFEC0'0000;
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constexpr uint64_t kIoApicData = 0xFEC0'0010;
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@ -88,7 +89,6 @@ void InspectApic() {
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dbgln("TPR: %x", GetLocalReg(0x80));
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dbgln("APR: %x", GetLocalReg(0x90));
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dbgln("PPR: %x", GetLocalReg(0xA0));
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dbgln("RRD: %x", GetLocalReg(0xC0));
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dbgln("LDR: %x", GetLocalReg(0xD0));
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dbgln("DFR: %x", GetLocalReg(0xE0));
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dbgln("SIV: %x", GetLocalReg(0xF0));
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@ -119,10 +119,22 @@ void EnableApic() {
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SetIoEntry(0x14, 0x20);
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// Skip Keyboard for now.
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// SetIoEntry(0x12, 0x21);
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// TODO: This also works with the interrupt numbers provided by the MADT
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// I need to do further investigation on the difference in this case and
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// also how to find a declarative spec for where the PCI Lines are mapped.
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// PCI Line 1-4
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// FIXME: These should be level triggered according to spec I believe
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// but because we handle the interrupt outside of the kernel it is tricky
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// to wait to send the end of interrupt message.
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// Because of this leave them as edge triggered and send EOI immediately.
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SetIoEntry(0x30, 0x30);
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SetIoEntry(0x32, 0x31);
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SetIoEntry(0x34, 0x32);
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SetIoEntry(0x36, 0x33);
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InspectApic();
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}
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void SignalEOI() {
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// Value doesn't matter.
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WriteLocalReg(kEoiOffset, 0x1);
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}
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void SignalEOI() { WriteLocalReg(kEoiOffset, 0x0); }
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@ -138,11 +138,44 @@ extern "C" void interrupt_timer(InterruptFrame*) {
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gScheduler->Preempt();
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}
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RefPtr<Port> pci1_port;
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extern "C" void isr_pci1();
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extern "C" void interrupt_pci1(InterruptFrame*) {
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dbgln("Interrupt PCI line 1");
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pci1_port->Write({});
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SignalEOI();
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}
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extern "C" void isr_pci2();
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extern "C" void interrupt_pci2(InterruptFrame*) {
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dbgln("Interrupt PCI line 2");
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SignalEOI();
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}
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extern "C" void isr_pci3();
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extern "C" void interrupt_pci3(InterruptFrame*) {
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dbgln("Interrupt PCI line 3");
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SignalEOI();
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}
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extern "C" void isr_pci4();
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extern "C" void interrupt_pci4(InterruptFrame*) {
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dbgln("Interrupt PCI line 4");
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SignalEOI();
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}
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void InitIdt() {
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gIdt[0] = CreateDescriptor(isr_divide_by_zero);
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gIdt[13] = CreateDescriptor(isr_protection_fault);
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gIdt[14] = CreateDescriptor(isr_page_fault);
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gIdt[32] = CreateDescriptor(isr_timer);
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gIdt[0x20] = CreateDescriptor(isr_timer);
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gIdt[0x30] = CreateDescriptor(isr_pci1);
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gIdt[0x31] = CreateDescriptor(isr_pci2);
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gIdt[0x32] = CreateDescriptor(isr_pci3);
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gIdt[0x33] = CreateDescriptor(isr_pci4);
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InterruptDescriptorTablePointer idtp{
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.size = sizeof(gIdt),
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.base = reinterpret_cast<uint64_t>(gIdt),
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@ -151,3 +184,5 @@ void InitIdt() {
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EnableApic();
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}
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void RegisterPciPort(const RefPtr<Port>& port) { pci1_port = port; }
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@ -1,3 +1,8 @@
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#pragma once
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#include "lib/ref_ptr.h"
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#include "object/port.h"
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void InitIdt();
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void RegisterPciPort(const RefPtr<Port>& port);
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@ -63,6 +63,34 @@ class PhysicalMemoryManager {
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}
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return page;
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}
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uint64_t AllocateContinuous(uint64_t num_pages) {
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if (front_ == nullptr) {
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panic("No available memory regions.");
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}
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if (front_->num_pages == 0) {
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panic("Bad state, empty memory block.");
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}
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MemBlock* block = front_;
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while (block != nullptr && block->num_pages < num_pages) {
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block = block->next;
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}
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if (block == nullptr) {
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panic("No memory regions to allocate");
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}
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uint64_t page = front_->base;
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front_->base += num_pages * 0x1000;
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front_->num_pages -= num_pages;
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if (front_->num_pages == 0) {
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MemBlock* temp = front_;
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front_ = front_->next;
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delete temp;
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}
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return page;
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}
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void FreePage(uint64_t page) { AddMemoryRegion(page, 0x1000); }
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private:
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@ -129,4 +157,12 @@ uint64_t AllocatePage() {
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return page;
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}
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uint64_t AllocateContinuous(uint64_t num_continuous) {
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if (gPmm == nullptr) {
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panic("No physical memory manager!");
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}
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return gPmm->AllocateContinuous(num_continuous);
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}
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} // namespace phys_mem
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@ -13,6 +13,7 @@ void InitBootstrapPageAllocation();
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void InitPhysicalMemoryManager();
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uint64_t AllocatePage();
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uint64_t AllocateContinuous(uint64_t num_pages);
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void FreePage(uint64_t page);
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} // namespace phys_mem
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@ -35,6 +35,7 @@ class MemoryObject : public KernelObject {
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class FixedMemoryObject : public MemoryObject {
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public:
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// FIXME: Validate that this is 4k aligned.
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FixedMemoryObject(uint64_t physical_addr, uint64_t size)
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: MemoryObject(size, true), physical_addr_(physical_addr) {}
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50
zion/object/port.cpp
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50
zion/object/port.cpp
Normal file
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@ -0,0 +1,50 @@
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#include "object/port.h"
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Port::Port() {}
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z_err_t Port::Write(const ZMessage& msg) {
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if (msg.num_caps > 0) {
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dbgln("Unimplemented passing caps on port");
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return Z_ERR_UNIMPLEMENTED;
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}
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if (msg.num_bytes > 0x1000) {
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dbgln("Large message size unimplemented: %x", msg.num_bytes);
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return Z_ERR_INVALID;
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}
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Message message{
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.type = msg.type,
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.num_bytes = msg.num_bytes,
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.bytes = new uint8_t[msg.num_bytes],
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};
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for (uint64_t i = 0; i < msg.num_bytes; i++) {
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message.bytes[i] = msg.bytes[i];
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}
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pending_messages_.PushBack(message);
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return Z_OK;
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}
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z_err_t Port::Read(ZMessage& msg) {
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if (pending_messages_.size() < 1) {
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dbgln("Implement blocking");
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return Z_ERR_UNIMPLEMENTED;
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}
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Message next_msg = pending_messages_.PeekFront();
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if (next_msg.num_bytes > msg.num_bytes) {
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return Z_ERR_BUFF_SIZE;
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}
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msg.type = next_msg.type;
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msg.num_bytes = next_msg.num_bytes;
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msg.num_caps = 0;
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for (uint64_t i = 0; i < msg.num_bytes; i++) {
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msg.bytes[i] = next_msg.bytes[i];
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}
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pending_messages_.PopFront();
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return Z_OK;
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}
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22
zion/object/port.h
Normal file
22
zion/object/port.h
Normal file
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@ -0,0 +1,22 @@
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#pragma once
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#include "lib/linked_list.h"
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#include "object/kernel_object.h"
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#include "usr/zcall_internal.h"
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class Port : public KernelObject {
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public:
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Port();
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z_err_t Write(const ZMessage& msg);
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z_err_t Read(ZMessage& msg);
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private:
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struct Message {
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uint64_t type;
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uint64_t num_bytes;
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uint8_t* bytes;
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};
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LinkedList<Message> pending_messages_;
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};
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@ -127,6 +127,13 @@ uint64_t Process::AddCapability(const RefPtr<Channel>& chan) {
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return cap_id;
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}
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uint64_t Process::AddCapability(const RefPtr<Port>& port) {
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uint64_t cap_id = next_cap_id_++;
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caps_.PushBack(MakeRefCounted<Capability>(port, Capability::PORT, cap_id,
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ZC_WRITE | ZC_READ));
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return cap_id;
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}
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void Process::AddCapability(uint64_t cap_id, const RefPtr<MemoryObject>& vmmo) {
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caps_.PushBack(MakeRefCounted<Capability>(vmmo, Capability::MEMORY_OBJECT,
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cap_id, ZC_WRITE));
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@ -7,6 +7,7 @@
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#include "lib/ref_ptr.h"
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#include "object/address_space.h"
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#include "object/channel.h"
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#include "object/port.h"
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// Forward decl due to cyclic dependency.
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class Thread;
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@ -37,6 +38,7 @@ class Process : public KernelObject {
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uint64_t AddCapability(const RefPtr<AddressSpace>& vmas);
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uint64_t AddCapability(const RefPtr<MemoryObject>& vmmo);
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uint64_t AddCapability(const RefPtr<Channel>& chan);
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uint64_t AddCapability(const RefPtr<Port>& chan);
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void AddCapability(uint64_t cap_id, const RefPtr<MemoryObject>& vmmo);
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// Checks the state of all child threads and transitions to
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@ -40,11 +40,13 @@ void Scheduler::Preempt() {
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if (current_thread_ == sleep_thread_) {
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// Sleep should never be preempted. (We should yield it if another thread
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// becomes scheduleable).
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asm volatile("sti");
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return;
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}
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if (runnable_threads_.size() == 0) {
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// Continue.
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asm volatile("sti");
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return;
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}
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@ -7,7 +7,10 @@
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#include "debug/debug.h"
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#include "include/zcall.h"
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#include "include/zerrors.h"
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#include "interrupt/interrupt.h"
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#include "memory/physical_memory.h"
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#include "object/channel.h"
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#include "object/port.h"
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#include "object/process.h"
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#include "scheduler/process_manager.h"
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#include "scheduler/scheduler.h"
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@ -131,11 +134,16 @@ z_err_t MemoryObjectCreate(ZMemoryObjectCreateReq* req,
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}
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z_err_t MemoryObjectCreatePhysical(ZMemoryObjectCreatePhysicalReq* req,
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ZMemoryObjectCreateResp* resp) {
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ZMemoryObjectCreatePhysicalResp* resp) {
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auto& curr_proc = gScheduler->CurrentProcess();
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auto vmmo_ref = MakeRefCounted<FixedMemoryObject>(req->paddr, req->size);
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uint64_t paddr = req->paddr;
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if (paddr == 0) {
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paddr = phys_mem::AllocateContinuous((req->size - 1 / 0x1000) + 1);
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}
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auto vmmo_ref = MakeRefCounted<FixedMemoryObject>(paddr, req->size);
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resp->vmmo_cap =
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curr_proc.AddCapability(StaticCastRefPtr<MemoryObject>(vmmo_ref));
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resp->paddr = paddr;
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return Z_OK;
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}
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@ -174,7 +182,30 @@ z_err_t ChannelRecv(ZChannelRecvReq* req) {
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RET_ERR(ValidateCap(chan_cap, Capability::CHANNEL, ZC_READ));
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auto chan = chan_cap->obj<Channel>();
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chan->Read(req->message);
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return chan->Read(req->message);
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}
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z_err_t PortRecv(ZPortRecvReq* req) {
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auto& proc = gScheduler->CurrentProcess();
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dbgln("Port cap %u", req->port_cap);
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auto port_cap = proc.GetCapability(req->port_cap);
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RET_ERR(ValidateCap(port_cap, Capability::PORT, ZC_READ));
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auto port = port_cap->obj<Port>();
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return port->Read(req->message);
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}
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z_err_t IrqRegister(ZIrqRegisterReq* req, ZIrqRegisterResp* resp) {
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auto& proc = gScheduler->CurrentProcess();
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if (req->irq_num != Z_IRQ_PCI_BASE) {
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// FIXME: Don't hardcode this nonsense.
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dbgln("Irq %x", req->irq_num);
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return Z_ERR_UNIMPLEMENTED;
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}
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RefPtr<Port> port = MakeRefCounted<Port>();
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resp->port_cap = proc.AddCapability(port);
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dbgln("Port cap %u", resp->port_cap);
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RegisterPciPort(port);
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return Z_OK;
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}
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@ -210,7 +241,7 @@ extern "C" z_err_t SyscallHandler(uint64_t call_id, void* req, void* resp) {
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case Z_MEMORY_OBJECT_CREATE_PHYSICAL:
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return MemoryObjectCreatePhysical(
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reinterpret_cast<ZMemoryObjectCreatePhysicalReq*>(req),
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reinterpret_cast<ZMemoryObjectCreateResp*>(resp));
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reinterpret_cast<ZMemoryObjectCreatePhysicalResp*>(resp));
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case Z_TEMP_PCIE_CONFIG_OBJECT_CREATE:
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return TempPcieConfigObjectCreate(
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reinterpret_cast<ZTempPcieConfigObjectCreateResp*>(resp));
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@ -220,6 +251,11 @@ extern "C" z_err_t SyscallHandler(uint64_t call_id, void* req, void* resp) {
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return ChannelSend(reinterpret_cast<ZChannelSendReq*>(req));
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case Z_CHANNEL_RECV:
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return ChannelRecv(reinterpret_cast<ZChannelRecvReq*>(req));
|
||||
case Z_PORT_RECV:
|
||||
return PortRecv(reinterpret_cast<ZPortRecvReq*>(req));
|
||||
case Z_IRQ_REGISTER:
|
||||
return IrqRegister(reinterpret_cast<ZIrqRegisterReq*>(req),
|
||||
reinterpret_cast<ZIrqRegisterResp*>(resp));
|
||||
case Z_DEBUG_PRINT:
|
||||
dbgln("[Debug] %s", req);
|
||||
return Z_OK;
|
||||
|
|
|
|||
|
|
@ -90,12 +90,25 @@ z_err_t ZMemoryObjectCreatePhysical(uint64_t paddr, uint64_t size,
|
|||
.paddr = paddr,
|
||||
.size = size,
|
||||
};
|
||||
ZMemoryObjectCreateResp resp;
|
||||
ZMemoryObjectCreatePhysicalResp resp;
|
||||
z_err_t ret = SysCall2(Z_MEMORY_OBJECT_CREATE_PHYSICAL, &req, &resp);
|
||||
*vmmo_cap = resp.vmmo_cap;
|
||||
return ret;
|
||||
}
|
||||
|
||||
z_err_t ZMemoryObjectCreateContiguous(uint64_t size, uint64_t* vmmo_cap,
|
||||
uint64_t* paddr) {
|
||||
ZMemoryObjectCreatePhysicalReq req{
|
||||
.paddr = 0,
|
||||
.size = size,
|
||||
};
|
||||
ZMemoryObjectCreatePhysicalResp resp;
|
||||
z_err_t ret = SysCall2(Z_MEMORY_OBJECT_CREATE_PHYSICAL, &req, &resp);
|
||||
*vmmo_cap = resp.vmmo_cap;
|
||||
*paddr = resp.paddr;
|
||||
return ret;
|
||||
}
|
||||
|
||||
z_err_t ZTempPcieConfigObjectCreate(uint64_t* vmmo_cap, uint64_t* vmmo_size) {
|
||||
ZTempPcieConfigObjectCreateResp resp;
|
||||
z_err_t ret = SysCall2(Z_TEMP_PCIE_CONFIG_OBJECT_CREATE, 0, &resp);
|
||||
|
|
@ -150,4 +163,35 @@ z_err_t ZChannelRecv(uint64_t chan_cap, uint64_t num_bytes, uint8_t* bytes,
|
|||
return ret;
|
||||
}
|
||||
|
||||
z_err_t ZPortRecv(uint64_t port_cap, uint64_t num_bytes, uint8_t* bytes,
|
||||
uint64_t num_caps, uint64_t* caps, uint64_t* type,
|
||||
uint64_t* actual_bytes, uint64_t* actual_caps) {
|
||||
ZPortRecvReq req{
|
||||
.port_cap = port_cap,
|
||||
.message =
|
||||
{
|
||||
.type = 0,
|
||||
.num_bytes = num_bytes,
|
||||
.bytes = bytes,
|
||||
.num_caps = num_caps,
|
||||
.caps = caps,
|
||||
},
|
||||
};
|
||||
z_err_t ret = SysCall1(Z_PORT_RECV, &req);
|
||||
*type = req.message.type;
|
||||
*actual_bytes = req.message.num_bytes;
|
||||
*actual_caps = req.message.num_caps;
|
||||
return ret;
|
||||
}
|
||||
|
||||
z_err_t ZIrqRegister(uint64_t irq_num, uint64_t* port_cap) {
|
||||
ZIrqRegisterReq req{
|
||||
.irq_num = irq_num,
|
||||
};
|
||||
ZIrqRegisterResp resp;
|
||||
z_err_t ret = SysCall2(Z_IRQ_REGISTER, &req, &resp);
|
||||
*port_cap = resp.port_cap;
|
||||
return ret;
|
||||
}
|
||||
|
||||
z_err_t ZDebug(const char* message) { return SysCall1(Z_DEBUG_PRINT, message); }
|
||||
|
|
|
|||
|
|
@ -51,6 +51,11 @@ struct ZMemoryObjectCreatePhysicalReq {
|
|||
uint64_t size;
|
||||
};
|
||||
|
||||
struct ZMemoryObjectCreatePhysicalResp {
|
||||
uint64_t vmmo_cap;
|
||||
uint64_t paddr;
|
||||
};
|
||||
|
||||
struct ZTempPcieConfigObjectCreateResp {
|
||||
uint64_t vmmo_cap;
|
||||
uint64_t vmmo_size;
|
||||
|
|
@ -80,3 +85,16 @@ struct ZChannelRecvReq {
|
|||
uint64_t chan_cap;
|
||||
ZMessage message;
|
||||
};
|
||||
|
||||
struct ZPortRecvReq {
|
||||
uint64_t port_cap;
|
||||
ZMessage message;
|
||||
};
|
||||
|
||||
struct ZIrqRegisterReq {
|
||||
uint64_t irq_num;
|
||||
};
|
||||
|
||||
struct ZIrqRegisterResp {
|
||||
uint64_t port_cap;
|
||||
};
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue