Rust XHCI Implementation.

This commit is contained in:
Drew 2025-12-05 22:01:13 -08:00
parent 0b95098748
commit 1b2ca34dd5
23 changed files with 707 additions and 110 deletions

View file

@ -78,6 +78,10 @@ impl MemoryRegion {
})
}
pub fn vaddr(&self) -> usize {
self.virt_addr as usize
}
pub fn slice<T>(&self) -> &[T] {
unsafe {
slice::from_raw_parts(
@ -246,11 +250,11 @@ pub fn map_cap_and_leak(mem_cap: Capability) -> u64 {
vaddr
}
pub fn map_direct_physical_and_leak(paddr: u64, size: u64) -> u64 {
pub fn map_direct_physical_and_leak<T>(paddr: u64, size: u64) -> *mut T {
let mem_cap = syscall::memory_object_direct_physical(paddr, size).unwrap();
let vaddr = syscall::address_space_map(&mem_cap).unwrap();
mem_cap.release();
vaddr
vaddr as *mut T
}
pub fn map_physical_and_leak(size: u64) -> (u64, u64) {

View file

@ -54,6 +54,12 @@ impl<T> PhysicalBox<[T]> {
let (memory_region, paddr) =
MemoryRegion::contiguous_physical(layout.size() as u64).expect("Failed to allocate");
crate::debug!(
"Physical box allocated: v {:0x} p {:0x}",
memory_region.vaddr(),
paddr
);
let ptr: *mut T = memory_region.mut_ptr_at_offset(0);
for i in 0..len {
unsafe {

View file

@ -72,15 +72,15 @@ impl PciDevice {
control.capable_address_64(),
"We don't handle the non-64bit case for MSI yet."
);
assert!(
control.multi_message_capable() == 0,
"We don't yet handle multi-message capable devices."
);
if control.multi_message_capable() != 0 {
mammoth::debug!("WARN: We don't yet handle multi-message capable devices.");
}
// FIXME: These probably need to be volatile writes.
let header: &mut PciDeviceHeader = self.memory_region.as_mut();
header.command = header.command.with_interrupt_disable(true);
msi_cap.msi_control = control.with_msi_enable(true);
msi_cap.msi_control = control.with_msi_enable(true).with_multi_message_enable(0);
// For setting addr and data field, see intel ref
// Vol 3. Section 11.11