[Denali] Reset AHCI controller when starting denali.
This commit is contained in:
Drew Galbraith
parent
8adde27d9b
commit
c530921bda
8 changed files with 92 additions and 62 deletions
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@ -1,229 +0,0 @@
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#include "ahci/ahci_driver.h"
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#include <glacier/status/error.h>
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#include <glacier/status/error_or.h>
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#include <mammoth/util/debug.h>
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#include <stdint.h>
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#include <zcall.h>
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namespace {
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const uint64_t kGhc_InteruptEnable = 0x2;
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void interrupt_thread(void* void_driver) {
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AhciDriver* driver = static_cast<AhciDriver*>(void_driver);
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driver->InterruptLoop();
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crash("Driver returned from interrupt loop", glcr::INTERNAL);
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}
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} // namespace
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glcr::ErrorOr<glcr::UniquePtr<AhciDriver>> AhciDriver::Init(
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mmth::OwnedMemoryRegion&& pci_region) {
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glcr::UniquePtr<AhciDriver> driver(new AhciDriver(glcr::Move(pci_region)));
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// RET_ERR(driver->LoadCapabilities());
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RET_ERR(driver->LoadHbaRegisters());
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RET_ERR(driver->LoadDevices());
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RET_ERR(driver->RegisterIrq());
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// driver->DumpCapabilities();
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// driver->DumpPorts();
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return driver;
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}
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glcr::ErrorOr<AhciDevice*> AhciDriver::GetDevice(uint64_t id) {
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if (id >= 32) {
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return glcr::INVALID_ARGUMENT;
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}
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if (devices_[id] != nullptr && !devices_[id]->IsInit()) {
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return glcr::NOT_FOUND;
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}
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return devices_[id];
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}
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void AhciDriver::DumpCapabilities() {
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dbgln("AHCI Capabilities:");
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uint32_t caps = ahci_hba_->capabilities;
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if (caps & 0x20) {
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dbgln("External SATA");
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}
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if (caps & 0x40) {
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dbgln("Enclosure Management");
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}
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if (caps & 0x80) {
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dbgln("Command Completion Coalescing");
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}
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if (caps & 0x2000) {
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dbgln("Partial State Capable");
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}
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if (caps & 0x4000) {
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dbgln("Slumber state capable");
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}
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if (caps & 0x8000) {
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dbgln("PIO Multiple DRQ Block");
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}
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if (caps & 0x1'0000) {
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dbgln("FIS-Based Switching");
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}
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if (caps & 0x2'0000) {
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dbgln("Port Multiplier");
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}
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if (caps & 0x4'0000) {
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dbgln("AHCI mode only");
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}
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dbgln("Speed support: {}", (caps & 0xF0'0000) >> 20);
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if (caps & 0x100'0000) {
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dbgln("Command list override");
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}
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if (caps & 0x200'0000) {
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dbgln("Activity LED");
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}
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if (caps & 0x400'0000) {
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dbgln("Aggresive link power management");
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}
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if (caps & 0x800'0000) {
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dbgln("Staggered spin up");
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}
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if (caps & 0x1000'0000) {
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dbgln("Mechanical Switch Presence");
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}
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if (caps & 0x2000'0000) {
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dbgln("SNotification Register");
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}
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if (caps & 0x4000'0000) {
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dbgln("Native Command Queueing");
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}
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if (caps & 0x8000'0000) {
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dbgln("64bit Addressing");
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}
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// Secondary.
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caps = ahci_hba_->capabilities_ext;
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if (caps & 0x1) {
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dbgln("BIOS/OS handoff");
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}
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if (caps & 0x2) {
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dbgln("NVMHCI Present");
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}
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if (caps & 0x4) {
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dbgln("Auto partial to slumber tranisitions");
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}
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if (caps & 0x8) {
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dbgln("Device sleep");
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}
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if (caps & 0x10) {
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dbgln("Aggressive device sleep management");
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}
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dbgln("Control {x}", ahci_hba_->global_host_control);
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}
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void AhciDriver::DumpPorts() {
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for (uint64_t i = 0; i < 6; i++) {
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AhciDevice* dev = devices_[i];
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if (dev == nullptr || !dev->IsInit()) {
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continue;
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}
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dbgln("");
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dbgln("Port {}:", i);
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dev->DumpInfo();
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}
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}
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void AhciDriver::InterruptLoop() {
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dbgln("Starting interrupt loop");
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while (true) {
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uint64_t bytes, caps;
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check(ZPortRecv(irq_port_cap_, &bytes, nullptr, &caps, nullptr));
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for (uint64_t i = 0; i < 32; i++) {
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if (devices_[i] != nullptr && devices_[i]->IsInit() &&
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(ahci_hba_->interrupt_status & (1 << i))) {
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devices_[i]->HandleIrq();
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ahci_hba_->interrupt_status &= ~(1 << i);
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}
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}
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}
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}
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glcr::ErrorCode AhciDriver::LoadCapabilities() {
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if (!(pci_device_header_->status_reg & 0x10)) {
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dbgln("No caps!");
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return glcr::FAILED_PRECONDITION;
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}
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uint8_t* base = reinterpret_cast<uint8_t*>(pci_device_header_);
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uint16_t offset = pci_device_header_->cap_ptr;
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do {
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uint16_t* cap = reinterpret_cast<uint16_t*>(base + offset);
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switch (*cap & 0xFF) {
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case 0x01:
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dbgln("Power Management");
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break;
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case 0x05:
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dbgln("MSI");
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break;
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case 0x12:
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dbgln("SATA");
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break;
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default:
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dbgln("Unrecognized cap");
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break;
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}
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offset = (*cap & 0xFF00) >> 8;
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} while (offset);
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return glcr::OK;
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}
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glcr::ErrorCode AhciDriver::RegisterIrq() {
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if (pci_device_header_->interrupt_pin == 0) {
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crash("Can't register IRQ without a pin num", glcr::INVALID_ARGUMENT);
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}
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uint64_t irq_num = 0;
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switch (pci_device_header_->interrupt_pin) {
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case 1:
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irq_num = kZIrqPci1;
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break;
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case 2:
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irq_num = kZIrqPci2;
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break;
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case 3:
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irq_num = kZIrqPci3;
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break;
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case 4:
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irq_num = kZIrqPci4;
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break;
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}
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RET_ERR(ZIrqRegister(irq_num, &irq_port_cap_));
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irq_thread_ = Thread(interrupt_thread, this);
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ahci_hba_->global_host_control |= kGhc_InteruptEnable;
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return glcr::OK;
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}
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glcr::ErrorCode AhciDriver::LoadHbaRegisters() {
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ahci_region_ = mmth::OwnedMemoryRegion ::DirectPhysical(
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pci_device_header_->abar, 0x1100);
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ahci_hba_ = reinterpret_cast<AhciHba*>(ahci_region_.vaddr());
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num_ports_ = (ahci_hba_->capabilities & 0x1F) + 1;
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num_commands_ = ((ahci_hba_->capabilities & 0x1F00) >> 8) + 1;
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return glcr::OK;
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}
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glcr::ErrorCode AhciDriver::LoadDevices() {
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for (uint8_t i = 0; i < 32; i++) {
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if (!(ahci_hba_->port_implemented & (1 << i))) {
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devices_[i] = nullptr;
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continue;
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}
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uint64_t port_addr =
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reinterpret_cast<uint64_t>(ahci_hba_) + 0x100 + (0x80 * i);
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devices_[i] = new AhciDevice(reinterpret_cast<AhciPort*>(port_addr));
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}
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return glcr::OK;
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}
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