[Denali] Interrupts working in rust.
This commit is contained in:
Drew Galbraith
parent
df79233bbb
commit
d94f61511b
8 changed files with 654 additions and 123 deletions
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@ -1,61 +1,61 @@
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use bitfield_struct::bitfield;
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#[bitfield(u32)]
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struct AhciPortInterruptStatus {
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device_to_host_register_fis_interrupt: bool,
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pio_setup_fis_interrupt: bool,
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dma_setup_fis_interrupt: bool,
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set_device_bits_interrupt: bool,
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pub struct AhciPortInterruptStatus {
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pub device_to_host_register_fis_interrupt: bool,
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pub pio_setup_fis_interrupt: bool,
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pub dma_setup_fis_interrupt: bool,
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pub set_device_bits_interrupt: bool,
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#[bits(access = RO)]
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unknown_fis_interrupt: bool,
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descriptor_prossed: bool,
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pub unknown_fis_interrupt: bool,
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pub descriptor_prossed: bool,
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#[bits(access = RO)]
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port_connect_change_status: bool,
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device_mechanical_presence_status: bool,
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pub port_connect_change_status: bool,
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pub device_mechanical_presence_status: bool,
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#[bits(14)]
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__: u32,
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#[bits(access = RO)]
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phy_rdy_change_status: bool,
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incorrect_port_multiplier_status: bool,
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overflow_status: bool,
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pub phy_rdy_change_status: bool,
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pub incorrect_port_multiplier_status: bool,
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pub overflow_status: bool,
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__: bool,
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interface_non_fatal_error_status: bool,
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interface_fatal_error_status: bool,
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host_bus_data_error_status: bool,
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host_bus_fatal_error_status: bool,
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task_file_error_status: bool,
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cold_port_detect_status: bool,
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pub interface_non_fatal_error_status: bool,
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pub interface_fatal_error_status: bool,
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pub host_bus_data_error_status: bool,
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pub host_bus_fatal_error_status: bool,
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pub task_file_error_status: bool,
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pub cold_port_detect_status: bool,
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}
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#[bitfield(u32)]
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struct AhciPortInterruptEnable {
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device_to_host_register_fis_enable: bool,
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pio_setup_fis_enable: bool,
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dma_setup_fis_enable: bool,
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set_device_bits_fis_enable: bool,
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unknown_fis_enable: bool,
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descriptor_processed_enable: bool,
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port_change_enable: bool,
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device_mechanical_presence_enable: bool,
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pub struct AhciPortInterruptEnable {
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pub device_to_host_register_fis_enable: bool,
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pub pio_setup_fis_enable: bool,
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pub dma_setup_fis_enable: bool,
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pub set_device_bits_fis_enable: bool,
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pub unknown_fis_enable: bool,
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pub descriptor_processed_enable: bool,
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pub port_change_enable: bool,
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pub device_mechanical_presence_enable: bool,
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#[bits(14)]
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__: u32,
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phy_rdy_change_enable: bool,
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incorrect_port_multiplier_enable: bool,
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overflow_enable: bool,
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pub phy_rdy_change_enable: bool,
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pub incorrect_port_multiplier_enable: bool,
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pub overflow_enable: bool,
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__: bool,
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interface_non_fatal_error_enable: bool,
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interface_fatal_error_enable: bool,
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host_bus_data_error_enable: bool,
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host_bust_fatal_error_enable: bool,
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task_file_error_enable: bool,
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cold_presence_detect_enable: bool,
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pub interface_non_fatal_error_enable: bool,
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pub interface_fatal_error_enable: bool,
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pub host_bus_data_error_enable: bool,
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pub host_bust_fatal_error_enable: bool,
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pub task_file_error_enable: bool,
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pub cold_presence_detect_enable: bool,
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}
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#[repr(u8)]
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@ -87,50 +87,50 @@ impl InterfaceCommunicationControl {
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}
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#[bitfield(u32)]
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struct AhciPortCommandAndStatus {
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start: bool,
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spin_up_device: bool,
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power_on_device: bool,
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command_list_overide: bool,
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fis_recieve_enable: bool,
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pub struct AhciPortCommandAndStatus {
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pub start: bool,
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pub spin_up_device: bool,
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pub power_on_device: bool,
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pub command_list_overide: bool,
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pub fis_recieve_enable: bool,
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#[bits(3)]
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__: u8,
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#[bits(5, access = RO)]
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current_command_slot: u8,
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pub current_command_slot: u8,
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#[bits(access = RO)]
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mechanical_presence_switch_state: bool,
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pub mechanical_presence_switch_state: bool,
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#[bits(access = RO)]
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fis_receive_running: bool,
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pub fis_receive_running: bool,
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#[bits(access = RO)]
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command_list_running: bool,
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pub command_list_running: bool,
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#[bits(access = RO)]
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cold_presence_state: bool,
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port_multipler_attached: bool,
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pub cold_presence_state: bool,
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pub port_multipler_attached: bool,
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#[bits(access = RO)]
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hot_plug_capable_port: bool,
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pub hot_plug_capable_port: bool,
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#[bits(access = RO)]
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mechanical_presence_switch_attached_to_port: bool,
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pub mechanical_presence_switch_attached_to_port: bool,
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#[bits(access = RO)]
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cold_presence_detection: bool,
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pub cold_presence_detection: bool,
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#[bits(access = RO)]
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external_sata_port: bool,
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pub external_sata_port: bool,
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#[bits(access = RO)]
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fis_base_switch_capable: bool,
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automatic_partial_to_slumber_transitions_enable: bool,
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device_is_atapi: bool,
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drive_led_on_atapi_enable: bool,
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aggressive_power_link_management_enable: bool,
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aggressive_slumber_partial: bool,
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pub fis_base_switch_capable: bool,
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pub automatic_partial_to_slumber_transitions_enable: bool,
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pub device_is_atapi: bool,
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pub drive_led_on_atapi_enable: bool,
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pub aggressive_power_link_management_enable: bool,
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pub aggressive_slumber_partial: bool,
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#[bits(4)]
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interface_communication_control: InterfaceCommunicationControl,
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pub interface_communication_control: InterfaceCommunicationControl,
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}
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#[bitfield(u32)]
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struct AhciPortTaskFileData {
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pub struct AhciPortTaskFileData {
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#[bits(access = RO)]
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err_status: bool,
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#[bits(2, access = RO)]
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@ -149,9 +149,9 @@ struct AhciPortTaskFileData {
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__: u16,
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}
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#[derive(Debug)]
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#[derive(Copy, Clone, Debug, PartialEq)]
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#[repr(u8)]
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enum AhciDeviceDetection {
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pub enum AhciDeviceDetection {
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NoDevice = 0x0,
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NoCommunication = 0x1,
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CommunicationEstablished = 0x3,
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@ -171,9 +171,9 @@ impl AhciDeviceDetection {
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}
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}
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#[derive(Debug)]
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#[derive(Copy, Clone, Debug)]
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#[repr(u8)]
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enum AhciCurrentInterfaceSpeed {
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pub enum AhciCurrentInterfaceSpeed {
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NoDevice = 0x0,
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Gen1 = 0x1,
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Gen2 = 0x2,
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@ -193,9 +193,9 @@ impl AhciCurrentInterfaceSpeed {
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}
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}
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#[derive(Debug)]
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#[derive(Copy, Clone, Debug, PartialEq)]
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#[repr(u8)]
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enum AhciInterfacePowerManagement {
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pub enum AhciInterfacePowerManagement {
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NoDevice = 0x0,
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Active = 0x1,
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PartialPower = 0x2,
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@ -218,15 +218,16 @@ impl AhciInterfacePowerManagement {
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}
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#[bitfield(u32)]
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struct AhciSataStatus {
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#[derive(PartialEq)]
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pub struct AhciSataStatus {
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#[bits(4, access = RO)]
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device_detection: AhciDeviceDetection,
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pub device_detection: AhciDeviceDetection,
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#[bits(4, access = RO)]
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current_interface_speed: AhciCurrentInterfaceSpeed,
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pub current_interface_speed: AhciCurrentInterfaceSpeed,
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#[bits(4, access = RO)]
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interface_power_management: AhciInterfacePowerManagement,
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pub interface_power_management: AhciInterfacePowerManagement,
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#[bits(20)]
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__: u32,
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@ -283,7 +284,7 @@ impl AhciSpeedAllowed {
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}
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#[bitfield(u32)]
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struct AhciSataControl {
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pub struct AhciSataControl {
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#[bits(4)]
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device_detection_initialization: AhciDeviceDetectionInitialization,
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@ -301,39 +302,39 @@ struct AhciSataControl {
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}
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#[bitfield(u32)]
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struct AhciSataError {
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recovered_data_integrity_error: bool,
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recovered_communications_error: bool,
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pub struct AhciSataError {
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pub recovered_data_integrity_error: bool,
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pub recovered_communications_error: bool,
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#[bits(6)]
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__: u8,
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transient_data_integrity_error: bool,
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persisten_communication_or_data_integrity_error: bool,
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protocol_error: bool,
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internal_error: bool,
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pub transient_data_integrity_error: bool,
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pub persisten_communication_or_data_integrity_error: bool,
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pub protocol_error: bool,
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pub internal_error: bool,
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#[bits(4)]
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__: u8,
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phy_ready_change: bool,
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phy_internal_error: bool,
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comm_wake: bool,
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decode_error: bool,
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pub phy_ready_change: bool,
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pub phy_internal_error: bool,
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pub comm_wake: bool,
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pub decode_error: bool,
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__: bool,
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crc_error: bool,
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handshake_error: bool,
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link_sequence_error: bool,
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transport_state_transition_error: bool,
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uknown_fis_type: bool,
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exchanged: bool,
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pub crc_error: bool,
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pub handshake_error: bool,
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pub link_sequence_error: bool,
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pub transport_state_transition_error: bool,
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pub uknown_fis_type: bool,
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pub exchanged: bool,
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#[bits(5)]
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__: u8,
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}
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#[bitfield(u32)]
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struct AhciFisBasedSwitchingControl {
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pub struct AhciFisBasedSwitchingControl {
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enable: bool,
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device_error_clear: bool,
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@ -357,7 +358,7 @@ struct AhciFisBasedSwitchingControl {
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}
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#[bitfield(u32)]
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struct AhciDeviceSleep {
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pub struct AhciDeviceSleep {
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aggressive_device_sleep_enable: bool,
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#[bits(access = RO)]
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@ -378,22 +379,25 @@ struct AhciDeviceSleep {
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__: u8,
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}
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#[derive(Debug)]
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#[repr(C, packed)]
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pub struct AhciPortHba {
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command_list_base: u64,
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fis_base: u64,
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interrupt_status: AhciPortInterruptStatus,
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interrupt_enable: AhciPortInterruptEnable,
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command: AhciPortCommandAndStatus,
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pub command_list_base: u64,
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pub fis_base: u64,
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pub interrupt_status: AhciPortInterruptStatus,
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pub interrupt_enable: AhciPortInterruptEnable,
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pub command: AhciPortCommandAndStatus,
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__: u32,
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task_file_data: AhciPortTaskFileData,
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signature: u32,
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sata_status: AhciSataStatus,
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sata_control: AhciSataControl,
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sata_error: AhciSataError,
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sata_active: u32,
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command_issue: u32,
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sata_notification: u32,
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fis_based_switching_ctl: AhciFisBasedSwitchingControl,
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device_sleep: AhciDeviceSleep,
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pub task_file_data: AhciPortTaskFileData,
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pub signature: u32,
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pub sata_status: AhciSataStatus,
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pub sata_control: AhciSataControl,
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pub sata_error: AhciSataError,
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pub sata_active: u32,
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pub command_issue: u32,
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pub sata_notification: u32,
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pub fis_based_switching_ctl: AhciFisBasedSwitchingControl,
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pub device_sleep: AhciDeviceSleep,
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}
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const _: () = assert!(size_of::<AhciPortHba>() == 0x48);
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