337 lines
18 KiB
Rust
337 lines
18 KiB
Rust
use bitfield_struct::bitfield;
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#[bitfield(u32)]
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pub struct HostControllerCapabilitiesLengthAndVersion {
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/// This register is used as an offset to add to register base to find the beginning of
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/// the Operational Register Space.
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#[bits(access=RO)]
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pub cap_length: u8,
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__: u8,
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/// This is a two-byte register containing a BCD encoding of the xHCI specification
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/// revision number supported by this host controller. The most significant byte of
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/// this register represents a major revision and the least significant byte contains
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/// the minor revision extensions. e.g. 0100h corresponds to xHCI version 1.0.0, or
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/// 0110h corresponds to xHCI version 1.1.0, etc
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#[bits(access=RO)]
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pub hci_version: u16,
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}
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#[bitfield(u32)]
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pub struct HCSParams1 {
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/// Number of Device Slots (MaxSlots). This field specifies the maximum number of Device
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/// Context Structures and Doorbell Array entries this host controller can support. Valid values are
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/// in the range of 1 to 255. The value of ‘0’ is reserved.
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#[bits(access=RO)]
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pub max_device_slots: u8,
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/// Number of Interrupters (MaxIntrs). This field specifies the number of Interrupters implemented
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/// on this host controller. Each Interrupter may be allocated to a MSI or MSI-X vector and controls
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/// its generation and moderation.
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///
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/// The value of this field determines how many Interrupter Register Sets are addressable in the
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/// Runtime Register Space (refer to section 5.5). Valid values are in the range of 1h to 400h. A ‘0’ in
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/// this field is undefined.
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#[bits(11, access=RO)]
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pub max_interrupters: u16,
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#[bits(5)]
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__: u8,
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/// Number of Ports (MaxPorts). This field specifies the maximum Port Number value, i.e. the
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/// highest numbered Port Register Set that are addressable in the Operational Register Space
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/// (refer to Table 5-18). Valid values are in the range of 1h to FFh.
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///
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/// The value in this field shall reflect the maximum Port Number value assigned by an xHCI
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/// Supported Protocol Capability, described in section 7.2. Software shall refer to these capabilities
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/// to identify whether a specific Port Number is valid, and the protocol supported by the
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/// associated Port Register Set.
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#[bits(access=RO)]
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pub max_ports: u8,
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}
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#[bitfield(u32)]
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pub struct HCSParams2 {
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/// Isochronous Scheduling Threshold (IST). Default = implementation dependent. The value in
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/// this field indicates to system software the minimum distance (in time) that it is required to stay
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/// ahead of the host controller while adding TRBs, in order to have the host controller process
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/// them at the correct time. The value shall be specified in terms of number of
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/// frames/microframes.
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///
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/// If bit [3] of IST is cleared to '0', software can add a TRB no later than IST[2:0] Microframes
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/// before that TRB is scheduled to be executed.
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///
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/// If bit [3] of IST is set to '1', software can add a TRB no later than IST[2:0] Frames before that TRB
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/// is scheduled to be executed.
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///
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/// Refer to Section 4.14.2 for details on how software uses this information for scheduling
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/// isochronous transfers.
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#[bits(4, access=RO)]
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pub isochronous_scheduling_threshold: u8,
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/// Event Ring Segment Table Max (ERST Max). Default = implementation dependent. Valid values
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/// are 0 – 15. This field determines the maximum value supported the Event Ring Segment Table
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/// Base Size registers (5.5.2.3.1), where:
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///
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/// The maximum number of Event Ring Segment Table entries = 2 ERST Max.
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/// e.g. if the ERST Max = 7, then the xHC Event Ring Segment Table(s) supports up to 128 entries,
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/// 15 then 32K entries, etc.
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#[bits(4, access=RO)]
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pub event_ring_segment_table_max: u8,
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#[bits(13)]
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__: u16,
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/// Max Scratchpad Buffers (Max Scratchpad Bufs Hi). Default = implementation dependent. This
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/// field indicates the high order 5 bits of the number of Scratchpad Buffers system software shall
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/// reserve for the xHC. Refer to section 4.20 for more information.
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#[bits(5, access=RO)]
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pub max_scratchpad_buffers_hi: u16,
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/// Scratchpad Restore (SPR). Default = implementation dependent. If Max Scratchpad Buffers is >
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/// ‘0’ then this flag indicates whether the xHC uses the Scratchpad Buffers for saving state when
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/// executing Save and Restore State operations. If Max Scratchpad Buffers is = ‘0’ then this flag
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/// shall be ‘0’. Refer to section 4.23.2 for more information.
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///
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/// A value of ‘1’ indicates that the xHC requires the integrity of the Scratchpad Buffer space to be
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/// maintained across power events.
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///
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/// A value of ‘0’ indicates that the Scratchpad Buffer space may be freed and reallocated between
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/// power events.
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#[bits(access=RO)]
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pub scratchpad_restore: bool,
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/// Max Scratchpad Buffers (Max Scratchpad Bufs Lo). Default = implementation dependent. Valid
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/// values for Max Scratchpad Buffers (Hi and Lo) are 0-1023. This field indicates the low order 5
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/// bits of the number of Scratchpad Buffers system software shall reserve for the xHC. Refer to
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/// section 4.20 for more information
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#[bits(5, access=RO)]
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pub max_scratchpad_buffers_lo: u16,
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}
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#[bitfield(u32)]
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pub struct HCSParams3 {
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/// U1 Device Exit Latency. Worst case latency to transition a root hub Port Link State (PLS) from
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/// U1 to U0. Applies to all root hub ports.
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/// The following are permissible values:
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///
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/// Value Description
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/// 00h Zero
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/// 01h Less than 1 μs
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/// 02h Less than 2 μs.
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/// …
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/// 0Ah Less than 10 μs
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#[bits(access=RO)]
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pub u1_device_exit_latency: u8,
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/// U2 Device Exit Latency. Worst case latency to transition from U2 to U0. Applies to all root hub
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/// ports.
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/// The following are permissible values:
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/// Value Description
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/// 0000h Zero
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/// 0001h Less than 1 μs.
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/// 0002h Less than 2 μs.
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/// …
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/// 07FFh Less than 2047 μs.
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/// 0800-FFFFh Reserved
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#[bits(access=RO)]
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pub u2_device_exit_latency: u8,
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__: u16,
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}
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#[bitfield(u32)]
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pub struct HCCParams1 {
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/// 64-bit Addressing Capability (AC64). This flag documents the addressing range capability of
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/// this implementation. The value of this flag determines whether the xHC has implemented the
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/// high order 32 bits of 64 bit register and data structure pointer fields. Values for this flag have the
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/// following interpretation:
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///
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/// Value Description
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/// 0 32-bit address memory pointers implemented
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/// 1 64-bit address memory pointers implemented
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///
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/// If 32-bit address memory pointers are implemented, the xHC shall ignore the high order 32 bits
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/// of 64 bit data structure pointer fields, and system software shall ignore the high order 32 bits of
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/// 64 bit xHC registers.
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#[bits(access=RO)]
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pub supports_64_bit: bool,
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/// BW Negotiation Capability (BNC). This flag identifies whether the xHC has implemented the
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/// Bandwidth Negotiation. Values for this flag have the following interpretation:
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///
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/// Value Description
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/// 0 BW Negotiation not implemented
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/// 1 BW Negotiation implemented
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///
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/// Refer to section 4.16 for more information on Bandwidth Negotiation.
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#[bits(access=RO)]
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pub bandwidth_negotiation: bool,
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/// Context Size (CSZ). If this bit is set to ‘1’, then the xHC uses 64 byte Context data structures. If
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/// this bit is cleared to ‘0’, then the xHC uses 32 byte Context data structures.
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/// Note: This flag does not apply to Stream Contexts.
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#[bits(access=RO)]
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pub context_size: bool,
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/// Port Power Control (PPC). This flag indicates whether the host controller implementation
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/// includes port power control. A ‘1’ in this bit indicates the ports have port power switches. A ‘0’ in
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/// this bit indicates the port do not have port power switches. The value of this flag affects the
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/// functionality of the PP flag in each port status and control register (refer to Section 5.4.8)
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#[bits(access=RO)]
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pub port_power_control: bool,
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/// Port Indicators (PIND). This bit indicates whether the xHC root hub ports support port indicator
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/// control. When this bit is a ‘1’, the port status and control registers include a read/writeable field
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/// for controlling the state of the port indicator. Refer to Section 5.4.8 for definition of the Port
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/// Indicator Control field.
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#[bits(access=RO)]
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pub port_indicators: bool,
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/// Light HC Reset Capability (LHRC). This flag indicates whether the host controller implementation
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/// supports a Light Host Controller Reset. A ‘1’ in this bit indicates that Light Host Controller Reset is
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/// supported. A ‘0’ in this bit indicates that Light Host Controller Reset is not supported. The value
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/// of this flag affects the functionality of the Light Host Controller Reset (LHCRST) flag in the
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/// USBCMD register (refer to Section 5.4.1).
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#[bits(access=RO)]
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pub light_hc_reset_capability: bool,
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/// Latency Tolerance Messaging Capability (LTC). This flag indicates whether the host controller
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/// implementation supports Latency Tolerance Messaging (LTM). A ‘1’ in this bit indicates that LTM
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/// is supported. A ‘0’ in this bit indicates that LTM is not supported. Refer to section 4.13.1 for more
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/// information on LTM
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#[bits(access=RO)]
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pub latency_tolerance_messaging_capability: bool,
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/// No Secondary SID Support (NSS). This flag indicates whether the host controller
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/// implementation supports Secondary Stream IDs. A ‘1’ in this bit indicates that Secondary Stream
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/// ID decoding is not supported. A ‘0’ in this bit indicates that Secondary Stream ID decoding is
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/// supported. (refer to Sections 4.12.2 and 6.2.3)
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#[bits(access=RO)]
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pub no_secondary_sid_support: bool,
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/// Parse All Event Data (PAE). This flag indicates whether the host controller implementation
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/// Parses all Event Data TRBs while advancing to the next TD after a Short Packet, or it skips all but
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/// the first Event Data TRB. A ‘1’ in this bit indicates that all Event Data TRBs are parsed. A ‘0’ in this
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/// bit indicates that only the first Event Data TRB is parsed (refer to section 4.10.1.1).
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#[bits(access=RO)]
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pub parse_all_event_data: bool,
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/// Stopped - Short Packet Capability (SPC). This flag indicates that the host controller
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/// implementation is capable of generating a Stopped - Short Packet Completion Code. Refer to
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/// section 4.6.9 for more information
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#[bits(access=RO)]
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pub stopped_short_packet_capability: bool,
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/// Stopped EDTLA Capability (SEC). This flag indicates that the host controller implementation
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/// Stream Context support a Stopped EDTLA field. Refer to sections 4.6.9, 4.12, and 6.4.4.1 for more
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/// information.
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/// Stopped EDTLA Capability support (i.e. SEC = '1') shall be mandatory for all xHCI 1.1 and xHCI 1.2
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/// compliant xHCs.
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#[bits(access=RO)]
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pub stopped_edtla_capability: bool,
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/// Contiguous Frame ID Capability (CFC). This flag indicates that the host controller
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/// implementation is capable of matching the Frame ID of consecutive Isoch TDs. Refer to section
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/// 4.11.2.5 for more information.
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#[bits(access=RO)]
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pub contiguous_frame_id_capability: bool,
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/// Maximum Primary Stream Array Size (MaxPSASize). This fields identifies the maximum size
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/// Primary Stream Array that the xHC supports. The Primary Stream Array size = 2MaxPSASize+1. Valid
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/// MaxPSASize values are 0 to 15, where ‘0’ indicates that Streams are not supported
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#[bits(4, access=RO)]
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pub maximum_primary_stream_array_size: u8,
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/// xHCI Extended Capabilities Pointer (xECP). This field indicates the existence of a capabilities list.
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/// The value of this field indicates a relative offset, in 32-bit words, from Base to the beginning of
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/// the first extended capability.
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///
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/// For example, using the offset of Base is 1000h and the xECP value of 0068h, we can calculated
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/// the following effective address of the first extended capability:
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/// 1000h + (0068h << 2) -> 1000h + 01A0h -> 11A0h
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#[bits(access=RO)]
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pub xhci_extended_capabilities_pointer: u16,
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}
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#[bitfield(u32)]
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pub struct HCCParams2 {
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/// U3 Entry Capability (U3C) - RO. This bit indicates whether the xHC Root Hub ports support port
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/// Suspend Complete notification. When this bit is '1', PLC shall be asserted on any transition of
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/// PLS to the U3 State. Refer to section 4.15.1 for more information.
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#[bits(access=RO)]
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pub u3_entry_capability: bool,
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/// Configure Endpoint Command Max Exit Latency Too Large Capability (CMC) - RO. This bit
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/// indicates whether a Configure Endpoint Command is capable of generating a Max Exit Latency
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/// Too Large Capability Error. When this bit is '1', a Max Exit Latency Too Large Capability Error
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/// may be returned by a Configure Endpoint Command. When this bit is '0', a Max Exit Latency Too
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/// Large Capability Error shall not be returned by a Configure Endpoint Command. This capability
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/// is enabled by the CME flag in the USBCMD register. Refer to sections 4.23.5.2 and 5.4.1 for more
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/// information.
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#[bits(access=RO)]
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pub configure_endpoint_command_max_exit_latency_too_large_capability: bool,
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/// Force Save Context Capability (FSC) - RO. This bit indicates whether the xHC supports the
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/// Force Save Context Capability. When this bit is '1', the Save State operation shall save any
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/// cached Slot, Endpoint, Stream or other Context information to memory. Refer to
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/// Implementation Note “FSC and Context handling by Save and Restore”, and sections 4.23.2 and
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/// 5.4.1 for more information.
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#[bits(access=RO)]
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pub force_save_context_capability: bool,
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/// Compliance Transition Capability (CTC) - RO. This bit indicates whether the xHC USB3 Root
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/// Hub ports support the Compliance Transition Enabled (CTE) flag. When this bit is ‘1’, USB3 Root
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/// Hub port state machine transitions to the Compliance substate shall be explicitly enabled
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/// software. When this bit is ‘0’, USB3 Root Hub port state machine transitions to the Compliance
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/// substate are automatically enabled. Refer to section 4.19.1.2.4.1 for more information.
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#[bits(access=RO)]
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pub compliance_transition_capability: bool,
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/// Large ESIT Payload Capability (LEC) - RO. This bit indicates whether the xHC supports ESIT
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/// Payloads greater than 48K bytes. When this bit is ‘1’, ESIT Payloads greater than 48K bytes are
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/// supported. When this bit is ‘0’, ESIT Payloads greater than 48K bytes are not supported. Refer to
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/// section 6.2.3.8 for more information.
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#[bits(access=RO)]
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pub large_esit_payload_capability: bool,
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/// Configuration Information Capability (CIC) - RO. This bit indicates if the xHC supports
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/// extended Configuration Information. When this bit is 1, the Configuration Value, Interface
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/// Number, and Alternate Setting fields in the Input Control Context are supported. When this bit is
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/// 0, the extended Input Control Context fields are not supported. Refer to section 6.2.5.1 for more
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/// information.
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#[bits(access=RO)]
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pub configuration_information_capability: bool,
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/// Extended TBC Capability78 (ETC) - RO. This bit indicates if the TBC field in an Isoch TRB
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/// supports the definition of Burst Counts greater than 65535 bytes. When this bit is ‘1’, the
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/// Extended EBC capability is supported by the xHC. When this bit is ‘0’, it is not. Refer to section
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/// 4.11.2.3 for more information.
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#[bits(access=RO)]
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pub extended_tbc_capability: bool,
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/// Extended TBC TRB Status Capability (ETC_TSC) - RO. This bit indicates if the TBC/TRBSts field
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/// in an Isoch TRB indicates additional information regarding TRB in the TD. When this bit is ‘1’, the
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/// Isoch TRB TD Size/TBC field presents TBC value and TBC/TRBSts field presents the TRBSts
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/// value. When this bit is ‘0’ then the ETC/ETE values defines the TD Size/TBC field and TBC/RsvdZ
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/// field. This capability shall be enabled only if LEC = ‘1’ and ETC=’1’. Refer to section 4.11.2.3 for
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/// more information.
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#[bits(access=RO)]
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pub extended_tbc_trb_status_capability: bool,
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/// Get/Set Extended Property Capability (GSC) – RO. This bit indicates support for the Set
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/// Extended Property and Get Extended Property commands. When this bit is ‘1’, the xHC supports
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/// the Get Extended Property and Set Extended Property commands defined in section 4.6.17 and
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/// section 4.6.18. When this bit is ‘0’, the xHC does not support the Get Extended Property and Set
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/// Extended Property commands and the xHC does not support any of the associated Extended
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/// Capabilities.
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///
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/// This bit shall only be set to ‘1’ if the xHC supports one or more extended capabilities that
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/// require the Get Extended Property and Set Extended Property commands.
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#[bits(access=RO)]
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pub get_set_extended_property_capability: bool,
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/// Virtualization Based Trusted I/O Capability (VTC) – RO. This bit when set to 1, indicates that
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/// the xHC supports the Virtualization based Trusted IO (VTIO) Capability. When this bit is 0, the
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/// VTIO Capability is not supported. This capability is enabled by the VTIOE flag in the USBCMD
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/// register.
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#[bits(access=RO)]
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pub virtualization_based_trusted_io_capability: bool,
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#[bits(22)]
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__: u32,
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}
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/// XHCI Spec Section 5.3
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/// Note that for 64 bit implementations, the controller requires qword (32bit) accesses.
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/// Hence the grouping of parameters here.
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///
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/// These registers are located at the addresses specified in BAR0 and BAR1 in the PCI Header.
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#[repr(C, packed)]
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pub struct HostControllerCapabilities {
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pub cap_length_and_version: HostControllerCapabilitiesLengthAndVersion,
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pub params_1: HCSParams1,
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pub params_2: HCSParams2,
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pub params_3: HCSParams3,
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pub cap_params_1: HCCParams1,
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/// This register defines the offset of the Doorbell Array base address from the Base. (RO)
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pub doorbell_offset: u32,
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/// This register defines the offset of the xHCI Runtime Registers from the Base.
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pub runtime_register_space_offset: u32,
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pub cap_params_2: HCCParams2,
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}
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const _: () = assert!(size_of::<HostControllerCapabilities>() == 0x20);
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