Rust XHCI Register Types.

rust/sys/voyageurs/src/xhci/registers/capabilities.rs

@@ -0,0 +1,337 @@
+use bitfield_struct::bitfield;
+
+#[bitfield(u32)]
+pub struct HostControllerCapabilitiesLengthAndVersion {
+    /// This register is used as an offset to add to register base to find the beginning of
+    /// the Operational Register Space.
+    #[bits(access=RO)]
+    pub cap_length: u8,
+    __: u8,
+    /// This is a two-byte register containing a BCD encoding of the xHCI specification
+    /// revision number supported by this host controller. The most significant byte of
+    /// this register represents a major revision and the least significant byte contains
+    /// the minor revision extensions. e.g. 0100h corresponds to xHCI version 1.0.0, or
+    /// 0110h corresponds to xHCI version 1.1.0, etc
+    #[bits(access=RO)]
+    pub hci_version: u16,
+}
+
+#[bitfield(u32)]
+pub struct HCSParams1 {
+    /// Number of Device Slots (MaxSlots). This field specifies the maximum number of Device
+    /// Context Structures and Doorbell Array entries this host controller can support. Valid values are
+    /// in the range of 1 to 255. The value of ‘0’ is reserved.
+    #[bits(access=RO)]
+    pub max_device_slots: u8,
+
+    /// Number of Interrupters (MaxIntrs). This field specifies the number of Interrupters implemented
+    /// on this host controller. Each Interrupter may be allocated to a MSI or MSI-X vector and controls
+    /// its generation and moderation.
+    ///
+    /// The value of this field determines how many Interrupter Register Sets are addressable in the
+    /// Runtime Register Space (refer to section 5.5). Valid values are in the range of 1h to 400h. A ‘0’ in
+    /// this field is undefined.
+    #[bits(11, access=RO)]
+    pub max_interrupters: u16,
+
+    #[bits(5)]
+    __: u8,
+    /// Number of Ports (MaxPorts). This field specifies the maximum Port Number value, i.e. the
+    /// highest numbered Port Register Set that are addressable in the Operational Register Space
+    /// (refer to Table 5-18). Valid values are in the range of 1h to FFh.
+    ///
+    /// The value in this field shall reflect the maximum Port Number value assigned by an xHCI
+    /// Supported Protocol Capability, described in section 7.2. Software shall refer to these capabilities
+    /// to identify whether a specific Port Number is valid, and the protocol supported by the
+    /// associated Port Register Set.
+    #[bits(access=RO)]
+    pub max_ports: u8,
+}
+
+#[bitfield(u32)]
+pub struct HCSParams2 {
+    /// Isochronous Scheduling Threshold (IST). Default = implementation dependent. The value in
+    /// this field indicates to system software the minimum distance (in time) that it is required to stay
+    /// ahead of the host controller while adding TRBs, in order to have the host controller process
+    /// them at the correct time. The value shall be specified in terms of number of
+    /// frames/microframes.
+    ///
+    /// If bit [3] of IST is cleared to '0', software can add a TRB no later than IST[2:0] Microframes
+    /// before that TRB is scheduled to be executed.
+    ///
+    /// If bit [3] of IST is set to '1', software can add a TRB no later than IST[2:0] Frames before that TRB
+    /// is scheduled to be executed.
+    ///
+    /// Refer to Section 4.14.2 for details on how software uses this information for scheduling
+    /// isochronous transfers.
+    #[bits(4, access=RO)]
+    pub isochronous_scheduling_threshold: u8,
+    /// Event Ring Segment Table Max (ERST Max). Default = implementation dependent. Valid values
+    /// are 0 – 15. This field determines the maximum value supported the Event Ring Segment Table
+    /// Base Size registers (5.5.2.3.1), where:
+    ///
+    /// The maximum number of Event Ring Segment Table entries = 2 ERST Max.
+    /// e.g. if the ERST Max = 7, then the xHC Event Ring Segment Table(s) supports up to 128 entries,
+    /// 15 then 32K entries, etc.
+    #[bits(4, access=RO)]
+    pub event_ring_segment_table_max: u8,
+
+    #[bits(13)]
+    __: u16,
+
+    /// Max Scratchpad Buffers (Max Scratchpad Bufs Hi). Default = implementation dependent. This
+    /// field indicates the high order 5 bits of the number of Scratchpad Buffers system software shall
+    /// reserve for the xHC. Refer to section 4.20 for more information.
+    #[bits(5, access=RO)]
+    pub max_scratchpad_buffers_hi: u16,
+
+    /// Scratchpad Restore (SPR). Default = implementation dependent. If Max Scratchpad Buffers is >
+    /// ‘0’ then this flag indicates whether the xHC uses the Scratchpad Buffers for saving state when
+    /// executing Save and Restore State operations. If Max Scratchpad Buffers is = ‘0’ then this flag
+    /// shall be ‘0’. Refer to section 4.23.2 for more information.
+    ///
+    /// A value of ‘1’ indicates that the xHC requires the integrity of the Scratchpad Buffer space to be
+    /// maintained across power events.
+    ///
+    /// A value of ‘0’ indicates that the Scratchpad Buffer space may be freed and reallocated between
+    /// power events.
+    #[bits(access=RO)]
+    pub scratchpad_restore: bool,
+
+    /// Max Scratchpad Buffers (Max Scratchpad Bufs Lo). Default = implementation dependent. Valid
+    /// values for Max Scratchpad Buffers (Hi and Lo) are 0-1023. This field indicates the low order 5
+    /// bits of the number of Scratchpad Buffers system software shall reserve for the xHC. Refer to
+    /// section 4.20 for more information
+    #[bits(5, access=RO)]
+    pub max_scratchpad_buffers_lo: u16,
+}
+
+#[bitfield(u32)]
+pub struct HCSParams3 {
+    /// U1 Device Exit Latency. Worst case latency to transition a root hub Port Link State (PLS) from
+    /// U1 to U0. Applies to all root hub ports.
+    /// The following are permissible values:
+    ///
+    /// Value Description
+    /// 00h Zero
+    /// 01h Less than 1 μs
+    /// 02h Less than 2 μs.
+    /// …
+    /// 0Ah Less than 10 μs
+    #[bits(access=RO)]
+    pub u1_device_exit_latency: u8,
+    /// U2 Device Exit Latency. Worst case latency to transition from U2 to U0. Applies to all root hub
+    /// ports.
+    /// The following are permissible values:
+    /// Value Description
+    /// 0000h Zero
+    /// 0001h Less than 1 μs.
+    /// 0002h Less than 2 μs.
+    /// …
+    /// 07FFh Less than 2047 μs.
+    /// 0800-FFFFh Reserved
+    #[bits(access=RO)]
+    pub u2_device_exit_latency: u8,
+    __: u16,
+}
+
+#[bitfield(u32)]
+pub struct HCCParams1 {
+    /// 64-bit Addressing Capability (AC64). This flag documents the addressing range capability of
+    /// this implementation. The value of this flag determines whether the xHC has implemented the
+    /// high order 32 bits of 64 bit register and data structure pointer fields. Values for this flag have the
+    /// following interpretation:
+    ///
+    /// Value Description
+    /// 0 32-bit address memory pointers implemented
+    /// 1 64-bit address memory pointers implemented
+    ///
+    /// If 32-bit address memory pointers are implemented, the xHC shall ignore the high order 32 bits
+    /// of 64 bit data structure pointer fields, and system software shall ignore the high order 32 bits of
+    /// 64 bit xHC registers.
+    #[bits(access=RO)]
+    pub supports_64_bit: bool,
+    /// BW Negotiation Capability (BNC). This flag identifies whether the xHC has implemented the
+    /// Bandwidth Negotiation. Values for this flag have the following interpretation:
+    ///
+    /// Value Description
+    /// 0 BW Negotiation not implemented
+    /// 1 BW Negotiation implemented
+    ///
+    /// Refer to section 4.16 for more information on Bandwidth Negotiation.
+    #[bits(access=RO)]
+    pub bandwidth_negotiation: bool,
+    /// Context Size (CSZ). If this bit is set to ‘1’, then the xHC uses 64 byte Context data structures. If
+    /// this bit is cleared to ‘0’, then the xHC uses 32 byte Context data structures.
+    /// Note: This flag does not apply to Stream Contexts.
+    #[bits(access=RO)]
+    pub context_size: bool,
+    /// Port Power Control (PPC). This flag indicates whether the host controller implementation
+    /// includes port power control. A ‘1’ in this bit indicates the ports have port power switches. A ‘0’ in
+    /// this bit indicates the port do not have port power switches. The value of this flag affects the
+    /// functionality of the PP flag in each port status and control register (refer to Section 5.4.8)
+    #[bits(access=RO)]
+    pub port_power_control: bool,
+    /// Port Indicators (PIND). This bit indicates whether the xHC root hub ports support port indicator
+    /// control. When this bit is a ‘1’, the port status and control registers include a read/writeable field
+    /// for controlling the state of the port indicator. Refer to Section 5.4.8 for definition of the Port
+    /// Indicator Control field.
+    #[bits(access=RO)]
+    pub port_indicators: bool,
+    /// Light HC Reset Capability (LHRC). This flag indicates whether the host controller implementation
+    /// supports a Light Host Controller Reset. A ‘1’ in this bit indicates that Light Host Controller Reset is
+    /// supported. A ‘0’ in this bit indicates that Light Host Controller Reset is not supported. The value
+    /// of this flag affects the functionality of the Light Host Controller Reset (LHCRST) flag in the
+    /// USBCMD register (refer to Section 5.4.1).
+    #[bits(access=RO)]
+    pub light_hc_reset_capability: bool,
+    /// Latency Tolerance Messaging Capability (LTC). This flag indicates whether the host controller
+    /// implementation supports Latency Tolerance Messaging (LTM). A ‘1’ in this bit indicates that LTM
+    /// is supported. A ‘0’ in this bit indicates that LTM is not supported. Refer to section 4.13.1 for more
+    /// information on LTM
+    #[bits(access=RO)]
+    pub latency_tolerance_messaging_capability: bool,
+    /// No Secondary SID Support (NSS). This flag indicates whether the host controller
+    /// implementation supports Secondary Stream IDs. A ‘1’ in this bit indicates that Secondary Stream
+    /// ID decoding is not supported. A ‘0’ in this bit indicates that Secondary Stream ID decoding is
+    /// supported. (refer to Sections 4.12.2 and 6.2.3)
+    #[bits(access=RO)]
+    pub no_secondary_sid_support: bool,
+    /// Parse All Event Data (PAE). This flag indicates whether the host controller implementation
+    /// Parses all Event Data TRBs while advancing to the next TD after a Short Packet, or it skips all but
+    /// the first Event Data TRB. A ‘1’ in this bit indicates that all Event Data TRBs are parsed. A ‘0’ in this
+    /// bit indicates that only the first Event Data TRB is parsed (refer to section 4.10.1.1).
+    #[bits(access=RO)]
+    pub parse_all_event_data: bool,
+    /// Stopped - Short Packet Capability (SPC). This flag indicates that the host controller
+    /// implementation is capable of generating a Stopped - Short Packet Completion Code. Refer to
+    /// section 4.6.9 for more information
+    #[bits(access=RO)]
+    pub stopped_short_packet_capability: bool,
+    /// Stopped EDTLA Capability (SEC). This flag indicates that the host controller implementation
+    /// Stream Context support a Stopped EDTLA field. Refer to sections 4.6.9, 4.12, and 6.4.4.1 for more
+    /// information.
+    /// Stopped EDTLA Capability support (i.e. SEC = '1') shall be mandatory for all xHCI 1.1 and xHCI 1.2
+    /// compliant xHCs.
+    #[bits(access=RO)]
+    pub stopped_edtla_capability: bool,
+    /// Contiguous Frame ID Capability (CFC). This flag indicates that the host controller
+    /// implementation is capable of matching the Frame ID of consecutive Isoch TDs. Refer to section
+    /// 4.11.2.5 for more information.
+    #[bits(access=RO)]
+    pub contiguous_frame_id_capability: bool,
+    /// Maximum Primary Stream Array Size (MaxPSASize). This fields identifies the maximum size
+    /// Primary Stream Array that the xHC supports. The Primary Stream Array size = 2MaxPSASize+1. Valid
+    /// MaxPSASize values are 0 to 15, where ‘0’ indicates that Streams are not supported
+    #[bits(4, access=RO)]
+    pub maximum_primary_stream_array_size: u8,
+    /// xHCI Extended Capabilities Pointer (xECP). This field indicates the existence of a capabilities list.
+    /// The value of this field indicates a relative offset, in 32-bit words, from Base to the beginning of
+    /// the first extended capability.
+    ///
+    /// For example, using the offset of Base is 1000h and the xECP value of 0068h, we can calculated
+    /// the following effective address of the first extended capability:
+    /// 1000h + (0068h << 2) -> 1000h + 01A0h -> 11A0h
+    #[bits(access=RO)]
+    pub xhci_extended_capabilities_pointer: u16,
+}
+
+#[bitfield(u32)]
+pub struct HCCParams2 {
+    /// U3 Entry Capability (U3C) - RO. This bit indicates whether the xHC Root Hub ports support port
+    /// Suspend Complete notification. When this bit is '1', PLC shall be asserted on any transition of
+    /// PLS to the U3 State. Refer to section 4.15.1 for more information.
+    #[bits(access=RO)]
+    pub u3_entry_capability: bool,
+    /// Configure Endpoint Command Max Exit Latency Too Large Capability (CMC) - RO. This bit
+    /// indicates whether a Configure Endpoint Command is capable of generating a Max Exit Latency
+    /// Too Large Capability Error. When this bit is '1', a Max Exit Latency Too Large Capability Error
+    /// may be returned by a Configure Endpoint Command. When this bit is '0', a Max Exit Latency Too
+    /// Large Capability Error shall not be returned by a Configure Endpoint Command. This capability
+    /// is enabled by the CME flag in the USBCMD register. Refer to sections 4.23.5.2 and 5.4.1 for more
+    /// information.
+    #[bits(access=RO)]
+    pub configure_endpoint_command_max_exit_latency_too_large_capability: bool,
+    /// Force Save Context Capability (FSC) - RO. This bit indicates whether the xHC supports the
+    /// Force Save Context Capability. When this bit is '1', the Save State operation shall save any
+    /// cached Slot, Endpoint, Stream or other Context information to memory. Refer to
+    /// Implementation Note “FSC and Context handling by Save and Restore”, and sections 4.23.2 and
+    /// 5.4.1 for more information.
+    #[bits(access=RO)]
+    pub force_save_context_capability: bool,
+    /// Compliance Transition Capability (CTC) - RO. This bit indicates whether the xHC USB3 Root
+    /// Hub ports support the Compliance Transition Enabled (CTE) flag. When this bit is ‘1’, USB3 Root
+    /// Hub port state machine transitions to the Compliance substate shall be explicitly enabled
+    /// software. When this bit is ‘0’, USB3 Root Hub port state machine transitions to the Compliance
+    /// substate are automatically enabled. Refer to section 4.19.1.2.4.1 for more information.
+    #[bits(access=RO)]
+    pub compliance_transition_capability: bool,
+    /// Large ESIT Payload Capability (LEC) - RO. This bit indicates whether the xHC supports ESIT
+    /// Payloads greater than 48K bytes. When this bit is ‘1’, ESIT Payloads greater than 48K bytes are
+    /// supported. When this bit is ‘0’, ESIT Payloads greater than 48K bytes are not supported. Refer to
+    /// section 6.2.3.8 for more information.
+    #[bits(access=RO)]
+    pub large_esit_payload_capability: bool,
+    /// Configuration Information Capability (CIC) - RO. This bit indicates if the xHC supports
+    /// extended Configuration Information. When this bit is 1, the Configuration Value, Interface
+    /// Number, and Alternate Setting fields in the Input Control Context are supported. When this bit is
+    /// 0, the extended Input Control Context fields are not supported. Refer to section 6.2.5.1 for more
+    /// information.
+    #[bits(access=RO)]
+    pub configuration_information_capability: bool,
+    /// Extended TBC Capability78 (ETC) - RO. This bit indicates if the TBC field in an Isoch TRB
+    /// supports the definition of Burst Counts greater than 65535 bytes. When this bit is ‘1’, the
+    /// Extended EBC capability is supported by the xHC. When this bit is ‘0’, it is not. Refer to section
+    /// 4.11.2.3 for more information.
+    #[bits(access=RO)]
+    pub extended_tbc_capability: bool,
+    /// Extended TBC TRB Status Capability (ETC_TSC) - RO. This bit indicates if the TBC/TRBSts field
+    /// in an Isoch TRB indicates additional information regarding TRB in the TD. When this bit is ‘1’, the
+    /// Isoch TRB TD Size/TBC field presents TBC value and TBC/TRBSts field presents the TRBSts
+    /// value. When this bit is ‘0’ then the ETC/ETE values defines the TD Size/TBC field and TBC/RsvdZ
+    /// field. This capability shall be enabled only if LEC = ‘1’ and ETC=’1’. Refer to section 4.11.2.3 for
+    /// more information.
+    #[bits(access=RO)]
+    pub extended_tbc_trb_status_capability: bool,
+    /// Get/Set Extended Property Capability (GSC) – RO. This bit indicates support for the Set
+    /// Extended Property and Get Extended Property commands. When this bit is ‘1’, the xHC supports
+    /// the Get Extended Property and Set Extended Property commands defined in section 4.6.17 and
+    /// section 4.6.18. When this bit is ‘0’, the xHC does not support the Get Extended Property and Set
+    /// Extended Property commands and the xHC does not support any of the associated Extended
+    /// Capabilities.
+    ///
+    /// This bit shall only be set to ‘1’ if the xHC supports one or more extended capabilities that
+    /// require the Get Extended Property and Set Extended Property commands.
+    #[bits(access=RO)]
+    pub get_set_extended_property_capability: bool,
+    /// Virtualization Based Trusted I/O Capability (VTC) – RO. This bit when set to 1, indicates that
+    /// the xHC supports the Virtualization based Trusted IO (VTIO) Capability. When this bit is 0, the
+    /// VTIO Capability is not supported. This capability is enabled by the VTIOE flag in the USBCMD
+    /// register.
+    #[bits(access=RO)]
+    pub virtualization_based_trusted_io_capability: bool,
+
+    #[bits(22)]
+    __: u32,
+}
+
+/// XHCI Spec Section 5.3
+/// Note that for 64 bit implementations, the controller requires qword (32bit) accesses.
+/// Hence the grouping of parameters here.
+///
+/// These registers are located at the addresses specified in BAR0 and BAR1 in the PCI Header.
+#[repr(C, packed)]
+pub struct HostControllerCapabilities {
+    pub cap_length_and_version: HostControllerCapabilitiesLengthAndVersion,
+    pub params_1: HCSParams1,
+    pub params_2: HCSParams2,
+    pub params_3: HCSParams3,
+    pub cap_params_1: HCCParams1,
+    /// This register defines the offset of the Doorbell Array base address from the Base. (RO)
+    pub doorbell_offset: u32,
+    /// This register defines the offset of the xHCI Runtime Registers from the Base.
+    pub runtime_register_space_offset: u32,
+    pub cap_params_2: HCCParams2,
+}
+
+const _: () = assert!(size_of::<HostControllerCapabilities>() == 0x20);